EDN

Lint tool checks constraint files

San Mateo, Calif. – Atrenta Inc. this week will introduce a new tool called SpyGlass Constraints that checks the completeness and consistency of synthesis and timing-tool constraint files to reduce ...
Design-Reuse

Zuken tool continues constraint-driven evolution

LONDON — Board-level EDA software vendor Zuken Ltd. plans to introduce Hot-Stage 4, the latest version of its virtual prototyping environment, at the Design Automation Conference next month. Hot-Stage ...
Semiconductor Engineering

Best Practices And Constraint Management Tools Speed RF Design For The IoT

The IoT has increased the demand for good radio frequency (RF) design practices from the mains, to wall outlet power, all the way to the antenna. With several IoT standards employed today, constraint ...
EDN

FPGA constraints for the modern world: Product how-to

Today’s FPGAs are larger and more complex than ever, and defining and applying correct design constraints is one of the biggest challenges. When the design fails to meet the timing performance ...
Semiconductor Engineering

Correct-By-Design Methodology Requires Carefully Defined Constraints

Since the dawn of PCB usage, constraints have been an important part of the design. What are the dimensions? What weight of copper? Now, constraints have become much more than just physical dimensions ...
Design-Reuse

Timing Aware Redundant Buffer Removal

With the common notion in VLSI world that power and area go side by side. When it comes to implementation and tool perspective there seems few factors which contradict the above statement. The well ...